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this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. for further information contact your local stmicroelectronics sales office. march 2012 doc id 022731 rev 2 1/17 1 STA8088FG fully integrated gps/galileo/glonass/qzss receiver with embedded rf and in-package flash data brief ? preliminary data features stmicroelectronics ? 3 rd generation positioning receiver with 32 tracking channels and 2 fast acquisition channels compatible with gps, galileo and glonass systems embedded rf front-end with separate gps/galieo/qzss and glonass if outputs embedded low noise amplifier -162 dbm indoor sensitivity (tracking mode) fast ttff < 1 s in hot start and 35 s in cold start high performance arm946 mcu (up to 208 mhz) 256 kbyte embedded sram in-package sqi flash memory (16 mbits) real time clock (rtc) circuit 32-bit watch-dog timer 3 uarts 1 i 2 c master/slave interface 1 synchronous serial port (ssp, motorola-spi supported) or 1 external sqi flash interface usb2.0 dual-role full speed (12 mhz) with integrated physical layer transceiver 2 controller area network (can) 2 channels adc (10 bits) 3 embedded 1.8 v voltage regulators i/o level selectable 1.8 v or 3.3 v operating condition: ?v dd12 : 1.2 v 10% ?v dd18/rf18 : 1.8 v 5% ?v lpvr 1.62 v to 3.6 v ?v ddio : 1.8 v 5%; 3.3 v 10% package: ? vfqfpn56 (7 x 7 x 0.85 mm) 0.4 mm pitch ambient temperature range: -40/+85c description STA8088FG is a single die standalone positioning receiver ic working on multiple constellations (gps/galileo/glonass/qzss). the minimum bom make STA8088FG the ideal solution for low-cost and small footprint products such handheld computers, cameras, data loggers, and sports accessories. the device is offered with a complete gnss firmware which performs all gnss operations including tracking, acquisition, navigation and data output with no need of external memories vfqfpn56 (7x7x0.85mm) www.st.com
contents STA8088FG 2/17 doc id 022666 rev 2 contents 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.2 vfqfpn56 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.3 power supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.4 main function pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.5 test/emulated dedicated pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.6 rf front-end pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.7 port 0 pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.8 port 1 pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3 package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1 ecopack ? packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2 vfqfpn56 7 x 7 x 0.85 mm package information . . . . . . . . . . . . . . . . . . 13 4 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
STA8088FG list of tables doc id 022666 rev 2 3/17 list of tables table 1. power supply pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 2. main function pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 3. test/emulated dedicated pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 4. rf front-end pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 5. port 0 pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 6. port 1 pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 7. vfqfpn56 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 8. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
list of figures STA8088FG 4/17 doc id 022666 rev 2 list of figures figure 1. STA8088FG system block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. vfqfpn56 connection diagram - with can (bottom view) . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 3. vfqfpn56 connection diagram - no can (bottom view). . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 4. vfqfpn56 7 x 7 x 0.85 mm package dimension. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 5. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
STA8088FG overview doc id 022666 rev 2 5/17 1 overview STA8088FG is a highly integrated system-on-chip device designed for positioning systems applications. the low power consumption and minimum bom make STA8088FG the ideal solution for low-cost and battery-operated portable products such handheld, computers, cameras, data loggers and sports accessories, as well as automotive application. it combines a high performance arm946 microprocessor with embedded enhanced peripherals and i/o capabilities with st next generation triple-constellation positioning engine. the rf front-end and base band processor are able to support gps/galileo and glonass navigation systems. the device is offered with a complete firmware which performs all positioning operations including tracking, acquisition, navigation and data output with no need of external memories. it also provides clock generation via pll, backup logic with real time clock and it supports usb2.0 standard at full speed, (12 mbps) with on-chip phy. STA8088FG is software compatible with the arm processor family. the device is power supplied with 1.8v and uses three on-chip voltage regulators to internally supply the rf front-end, core logic and the backup logic. in order to reduce the power consumption the chip can be directly powered with 1.2 v bypassing the embedded voltage regulators which will be put in power down mode. i/o lines are compatible with 1.8 v and 3.3 v. the chip, using stmicroelectronics cmosrf technology, is housed in a vfqfpn-56 (7 x 7 x 0.85 mm) package with stacked 16 mbit flash memory.
pin description STA8088FG 6/17 doc id 022666 rev 2 2 pin description 2.1 block diagram figure 1. STA8088FG system block diagram bk_dom a in s qi if u s b if vic rom 16kb ahb dcreg o s ci 3 2 th s en s s aradc ad10 s a1m_1 8 o s ci 3 2 o s ci 3 2_lj_1v 8 pwr, r s t & clk ctrl i s o cell i2c ss p uart2 rx - tx regmap apb bridge2 uart1 rx - tx uart rx-tx adc mtu gpio eft wd apb arm 946 i-c a che 16kb d-c a che 8 kb high s peed i - tcm 64kb 64khigh s peed d ? tcm 8 apb bridge1 s y s ctrl rtc apb ram 8 kb g 3 b as e b a nd glon ass if galgp s if 2 f as t ac q ch a nnel 3 2 trk ch a nnel s m u x ac q ram s apb bridge dc_ln_1v 8 to1v2 hpreg lpreg bkreg clock_gen ckx2 pll pg_650x frc_dpll rio s c47 te s t controller io s jtag g 3 rf ip 1. 8 v 1.2v dcreg s pi if o s ci 26mhz rf s ection lna s ection adc galgp s adc glona ss i/d s witchable tcm 8 x16kb gapgcft00542 can1 can0
STA8088FG pin description doc id 022666 rev 2 7/17 2.2 vfqfpn56 pin configuration figure 2. vfqfpn56 connection diagram - with can (bottom view) 4-3 4234n %0 6$$?-62 40?)&?0 40?)&?. 62&?2&!$# ,.!?). '.$?,.! ,.!?/54 62&/54?2&62 62&?2&62 62&?,.! 5!2 4?48"//4? 0 5!2 4?28 0 5!2 4?48"//4? 0 5!2 4?280 '0)/0 6$$?)/2 !$# ?). !$# ?). 6$$?-62 24#?84/ 6$$?,062 24#?84) 330?#3.0 330?$/0 330?$)0 330 ?#,+0 6$$?-62 53"?$05!24?4 8 53"?$-5!24?2 8 4$/ 6$$?)/2 4$) 4#+ 62&?2&! 2&!?). 62&?-)8 62&?)& 62&?2&6#/ 84!,?). 84!,?/54 6$$?,062 6$$?-62 34$"9n 234n 7!+%50 )#?3#,+#!.28 0 34$"9/54 6$$?-62 #!.48 )#?3$#!.48 0 #!. 28 6$$?)/2 6$$?)/2 '0)/0 ("1($'5
pin description STA8088FG 8/17 doc id 022666 rev 2 figure 3. vfqfpn56 connection diagram - no can (bottom view) 2.3 power supply pins 4-3 4234n %0 6$$?-62 40?)&?0 40?)&?. 62&?2&!$# ,.!?). '.$?,.! ,.!?/54 62&/54?2&62 62&?2&62 62&?,.! 5!2 4?48"//4?0 5!2 4?28 0 5!2 4?48"//4? 0 5!2 4?28 0 '0)/0 6$$?)/2 !$# ?). !$# ?). 6$$?-62 24#?84/ 6$$?,062 24#?84) 330?#3.0 330?$/0 330?$)0 330 ?#,+0 6$$?-62 53"?$05!24?48 53"?$-5!24?2 8 4$/ 6$$?)/2 4$) 4#+ 62&?2&! 2&!?). 62&?-)8 62&?)& 62&?2&6#/ 84!,?). 84!,?/54 6$$?,062 6$$?-62 34$"9n 234n 7!+%50 )#?3#,+ 0 34$"9/54 6$$?-62 .# )#?3$ 0 .# 6$$?)/2 6$$?)/2 '0)/0 ("1($'5 table 1. power supply pins symbol i/o functions vfqfn56 vdd18_mvr[1,2] pwr digital supply voltage for main voltage regulator (1.8 v) 31,4 vdd12_mvr[1,2,3] pwr digital supply voltage for core circuitry (1.2 v). when using the mvr, this pin shall not be driven by an external voltage supply, but a capacitance shall be connected between these pins and gnd to guarantee on-chip voltage stability. 22,47,30 vdd_lpvr pwr digital supply voltage for low power voltage regulator (1.62 - 3.6 v) 29
STA8088FG pin description doc id 022666 rev 2 9/17 2.4 main function pins vdd12_lpvr pwr digital supply voltage for backup logic (1.2 v). when using the lpvr, this pin shall not be driven by an external voltage supply, but a capacitance shall be connected between these pins and gnd to guarantee on-chip voltage stability. 21 vdd_ior1 pwr digital supply voltage for i/o ring 1 (1.8 or 3.3 v) 44 vdd_ior3 pwr digital supply voltage for i/o ring 3 (1.8 v) 45 vdd_ior4 pwr digital supply voltage for i/o ring 4 (1.8 v) 34 vdd_ior5 pwr digital supply voltage for i/o ring 5 (3.3 v) 52 vrf18_rfvr pwr analog supply voltage for rf voltage regulator (1.8 v) 13 vrf12out_rfvr pwr rf voltage regulator 1.2 v output 12 vrf12_lna pwr analog supply voltage for lna (1.2 v) 8 vrf12_rfa pwr analog supply voltage for rfa (1.2 v) 14 vrf12_mix pwr analog supply voltage for mixer (1.2 v) 16 vrf12_if pwr analog supply voltage for if (1.2 v) 17 vrf12_rfvco pwr analog supply voltage for vco (1.2 v) 18 vrf12_rfadc pwr analog supply voltage for rf adc (1.2 v) 7 gnd_lna gnd analog supply ground for lna 10 gnd gnd analog and digital supply ground ep table 1. power supply pins (continued) symbol i/o functions vfqfn56 table 2. main function pins symbol i/o voltage i/o functions vfqfpn56 stdbyn 1.2v i when low, the chip is forced in standby mode - all pins in high impedance except the ones powered by backup supply 24 stdbyout 1.2v o when low, indicates the chip is in standby mode. 23 rstn 1.2v i reset input with schmitt-trigger characteristics and noise filter. 25 wakeup 1.2v i wakeup from standby mode 26 rtc_xti 1.5v (max) i input of the 32 khz oscillator amplifier circuit and input of the internal real time clock circuit. 27 rtc_xto 1.5v (max) o output of the oscillator amplifier circuit. 28 adc_in[1,5] 1.4v ? 0 typ range i adc analog input [1,5] 32,33 usb_dp/uart1_tx vdd_ior5 usb/o usb d+ signal / uart 1 tx data 48 usb_dm/uart1_rx vdd_ior5 usb/i usb d- signal / uart 1 rx data 49
pin description STA8088FG 10/17 doc id 022666 rev 2 2.5 test/emulated dedicated pins 2.6 rf front-end pins 2.7 port 0 pins port 0 consists of a 32-bit bidirectional i/o port (only 3-bit are used in STA8088FG). it can be either used as general purpose input or output port, or configured according to the associated alternate functions. can0tx (1) vdd_ior5 o can0 - transmit data output 51 can0rx (1) vdd_ior5 i can0 - receive data input 54 1. only for STA8088FGb (see figure 5: ordering information scheme ). table 2. main function pins (continued) symbol i/o voltage i/o functions vfqfpn56 table 3. test/emulated dedicated pins symbol i/o voltage i/o functions vfqfpn56 tdo vdd_ior5 o jtag test data out 50 tdi vdd_ior5 i jtag test data in 53 tck vdd_ior5 i jtag test clock 56 tms vdd_ior5 i jtag test mode select 2 trstn vdd_ior5 i jtag test circuit reset 3 tp_if_p vrf12_if o diff. test point for if ? positive 5 tp_if_n vrf12_if o diff. test point for if ? negative 6 table 4. rf front-end pins symbol i/o voltage i/o functions vfqfpn56 lna_in vrf12_lna i low noise amplifier input 9 lna_out vrf12_lna o low noise amplifier output 11 rfa_in vrf12_rfa i rf amplifier input 15 xtal_in vrf12_rfdig i input side of crystal oscillator or tcxo input 19 xtal_out vrf12_rfdig o output side of crystal oscillator 20
STA8088FG pin description doc id 022666 rev 2 11/17 2.8 port 1 pins port 1 consists of a 32-bit bidirectional i/o port (only9-bit are used in STA8088FG). it can be either used as general purpose input or output port, or configured according to the associated alternate functions. table 5. port 0 pins symbol i/o voltage i/o mode functions vfqfpn56 p0.0 vdd_ior1 io default gpio.0: general purpose io 35 i a pps_in: pulse per second input o b pps_out: pulse per second output o c ssp_csn: ssp chip select active low p0.8 vdd_ior5 o default can1tx (1) : can1 transmit data output 55 io a gpio.8: general purpose io io b i2c_sd: i2c serial data p0.9 vdd_ior5 i default can1rx (1) : can 1 receive data input 1 io a gpio.9: general purpose io o b i2c_sclk: i2c clock 1. only for STA8088FGb (see figure 5: ordering information scheme ). table 6. port 1 pins symbol i/o voltage i/o mode functions vfqfpn56 p1.0 vdd_ior1 odefault ssp_csn/iopwrsel_r1: ssp chip select active low / i/o ring 1 power selection 40 i/o a gpio32: general purpose i/o i/o b signggps: ggps 3-bit coding output (sign) o c sqi_cen: sqi flash chip enable p1.1 vdd_ior1 i/o default ssp_clk: ssp clock 41 i/o a gpio33: general purpose i/o i/o b clock_ggps: ggps clock out o c sqi_clk: sqi flash clock p1.2 vdd_ior1 i default ssp_di: ssp serial data input 42 i/o a gpio34: general purpose i/o i/o b signgns: gns 3-bit coding output (sign) io c sqi_sio0/si: sqi flash data i/o 0 / serial i
pin description STA8088FG 12/17 doc id 022666 rev 2 p1.3 vdd_ior1 o default ssp_do: ssp serial data output 43 i/o a gpio35: general purpose i/o i/o b clock_gns: gns clock out io c sqi_sio1/so: sqi flash data i/o 1 / serial o p1.4 vdd_ior1 i default uart2_rx: uart 2 rx data 36 i/o a gpio36: general purpose i/o p1.5 vdd_ior1 i/o default uart2_tx / boot_0: uart 2 tx data / arm boot 0 37 i/o a gpio37: general purpose i/o p1.6 vdd_ior1 i default uart0_rx: uart 0 rx data 38 i/o a gpio38: general purpose i/o i/o c sqi_sio2: sqi flash data i/o 2 p1.7 vdd_ior1 i/o default uart0_tx / boot_1: uart 0 tx data / arm boot 1 39 i/o a gpio39: general purpose i/o i/o c sqi_sio3: sqi flash data i/o 3 p1.21 vdd_ior3 i/o a gpio53: general purpose i/o 46 table 6. port 1 pins (continued) symbol i/o voltage i/o mode functions vfqfpn56
STA8088FG package and packing information doc id 022666 rev 2 13/17 3 package and packing information 3.1 ecopack ? packages in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. 3.2 vfqfpn56 7x7x0.85mm package information table 7. vfqfpn56 package dimensions symbol min. typ. max common dimensions a 0.80 0.85 0.90 a1 0 0.01 0.05 a2 0.60 0.65 0.70 a3 0.20 ref b 0.15 0.20 0.25 d 7.00 bsc d1 6.75 bsc d2 5.0 5.1 5.2 e 7.00 bsc e1 6.75 bsc e2 5.0 5.1 5.2 e 0.40 bsc 0 12 l 0.30 0.40 0.50 n56 nd 14 ne 14 p 0.24 0.42 0.60 q 0.30 0.40 0.65 r 0.13 0.17 0.23
package and packing information STA8088FG 14/17 doc id 022666 rev 2 figure 4. vfqfpn56 7 x 7 x 0.85 mm package dimension ("1($'5
STA8088FG ordering information doc id 022666 rev 2 15/17 4 ordering information figure 5. ordering information scheme packing gnss can bus tr = tape and reel = tray b = yes = no g = gps/glonass/galileo/qzss = gps/qzss sal with stacked flash sta8088f tr g b example code: family identifier
revision history STA8088FG 16/17 doc id 022666 rev 2 5 revision history table 8. document revision history date revision changes 27-jan-2012 1 initial release. 07-mar-2012 2 updated features list updated following figures: ? figure 2: vfqfpn56 connection diagram - with can (bottom view) ? figure 3: vfqfpn56 connection diagram - no can (bottom view) table 2: main function pins : ? usb_dp/uart1_tx, usb_dm/uart1_rx: updated i/o
STA8088FG doc id 022666 rev 2 17/17 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a particular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by two authorized st representatives, st products are not recommended, authorized or warranted for use in military, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or register ed trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2012 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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